CPE-bus communication protocol is designed for high speed, high resolution encoder or linear scale interfacing. The key features of CPE-bus is high reliability and easy to use.
CPE-bus is the China’s recommended national industrial standard ( JB/T 11505-2013 ) for rotary encoders / linear scales communication which was pulished by the China Ministry of Industrial & Information on 2014, CPE-bus is a public standard which is totally royality & patent free, therefore, CPE-bus users are free from any unpleasant legal harassment from dominating companies.
- Rotary Encoders
- Linear Scales
- Auto vehicles
Main Features :
- Small in size and low cost, very efficient use of FPGA logic gate, only about 32,500 logic gates used.
- Auto CRC verifications, minimum effort to achieve the highest communication reliability.
- Flexible readout configuration, work for both interrupt or polling mode.
- High data update rate, 12.5K updates / sec.
- Flexible hardware configuration, it can work with CPE_TXD.v for bi-directional bus communication
CPE_RXD.v is a CPE-bus communication ASIC module IP core ( receiver side ) that designed and developed by Easson Measurement Technology Ltd. The purpose of CPE_RXD.v is to provide an easy, proven reliable interfaces to our customer to interface their CNC controller/servo driver to our linear scale or rotary encoder products.
Easson provides the CPE_RXD.v in FPGA source program ( Verilog ) , so that our customer can have it intergated and implemented in all types and all brands of FPGA/CPLD devices available in the market with only very small effort. Despite the CPE-bus communication have CRC mechanism, the normal engineering practise is to have such protocols being implemented by serveral independent modules which is simple in structure.
However, for the consideration in ease of implementation and to reduce number of logic gates used, one complete module design concept is used in CPE_RXD.v to make it very simple and easy to integrate into customers’ hardware system.
CPE_RXD.v is an proven and superior reliable communicationmodule IP core that have AUTO CRC verification. All CRC generations and verifcations are done by hardware in background without any involvement of the system CPU. Only the verified correct data shall appear in the STATUS[9:0] output bus and DATA[31:0] output bus.
CPE_RXD.v provides two modes of readout operation, they are Interrupt mode or Polling mode. For slow data rate ( data rate less than 1K/sec ), Interrupt mode is prefered in most caes. For high data rate ( data rate up to 12.5K/sec ) polling mode seems to be the only feasible way for data readout.
For more details, please download the PDF file: cpe-bus rxd.pdf
Contact Person: Tony